1. Technical Field
This invention relates generally to a method of fabricating a lateral PNP transistor, and in particular relates to a method of fabricating a lateral PNP transistor with a graded collector simultaneously with fabricating NPN transistors.
2. Prior Art
One type of transistor which has found wide application in integrated circuits is the lateral PNP transistor. In this type of transistor, two regions near the surface of a semiconducting material are doped P-type and form respectively the emitter and collector. The emitter and collector are separated along the surface by an N-type region, which forms the base of the transistor. In order to obtain high operating speeds, the base is made as narrow as possible. However, two problems ensue. If the base-collector junction is reverse-biased, the depletion region extends into the narrow base region and at a punch-through voltage will extend through the base to the emitter. Once the depletion region has punched through, current control of the transistor is lost. If however, the depletion width is maintained relatively narrow for a given voltage by increasing the doping level of the base region, the resultant high electric field in the depletion region may exceed the electric field for avalanche breakdown. The current multiplication associated with avalanche also destroys current control.
The fabrication of PNP transistors becomes particularly difficult when they are to be included in an integrated circuit fabricated with an NPN technology. That is, the integrated circuit is to include both NPN and PNP transistors. As with any integrated circuit method, the number of processing steps and particularly of mask levels should be minimized. The necessity for simultaneously fabricating both NPN and PNP transistors has caused design trade-offs which sacrifice the performance of the PNP transistors built.
A typical processing sequence for fabricating a conventional vertical NPN bipolar transistor will now be described. As shown in FIG. 1, a P-type silicon substrate 20 is overlaid with an oxide layer 22 which is etched to provide a collector window 24 and an isolation window 26 surrounding the collector window 24. Then with a series of photo-resist masking steps and diffusion steps, an N.sup.+ sub-collector 28 and a P.sup.+ isolation region 30 are formed on the surface of the substrate 20. Thereafter the oxide layer 22 is stripped and an N.sup.- epitaxial layer 32 is grown, as shown in FIG. 2.
Thereafter, as shown in FIG. 3, additional masking and diffusion steps are used to diffuse N-type and P-type dopants from the surface to form an N.sup.+ sub-collector reach-through 34 that joins the N.sup.+ sub-collector 28 and to form a larger P.sup.+ isolation region 36. An isolated N.sup.- region 74 is isolated from the sub-collector 28 by the isolation region 36. A field oxide 38 is grown on top of this structure that has a thickness greater over the P.sup.+ isolation region 36. Then, as shown in FIG. 4, ion implantation is used to form a P-type base P(B) 40 at the surface of a part of the N.sup.+ sub-collector 28 within the isolation region 36. The ion implantation is done through the field oxide 38 and the resultant base 40 further defines an N.sup.- collector 42. The field oxide 38 serves to protect the surface of ion-implanted regions.
A blocking mask 44 of photo-resist is used as shown in FIG. 5 to cover the transistor region within the P.sup.+ isolation region 36 and thereafter another ion implantation of P-type dopants is performed through the field oxide 38 to form a P-type resistor P(R) 46. As shown in FIG. 6, with yet another mask and another ion implantation through the field oxide 38, P-type dopants are used to form a P.sup.+ base contact 48 and a P.sup.+ resistor contact 50, as shown in FIG. 6.
Then, as shown in FIG. 7, an N.sup.+ dopant is diffused into the base 40 to form an N.sup.+ emitter 52. The result is a vertical NPN transistor between the emitter 52, the base 40 and the collector 42. The field oxide is preferentially etched above the base contact 48 part of the base 40, above the emitter 52, above the N.sup.+ sub-collector reach-through 34 and above the base contact 50. Finally, interconnection metallurgy is evaporated onto the surface in a predetermined pattern to form a base lead 54, an emitter lead 56, a collector lead 58 and a resistor lead 60.
Although methods are known to fabricate PNP transistors and particularly lateral PNP transistors within this sequence of NPN fabrication steps, these transistors have suffered the previously described problems of low punch-through voltage, low avalanche breakdown voltage or poor performance as measured by gain and frequency response.
Methods have been described which increase the performance of transistors by providing graded doping within the base region. Such a method has been described for a lateral PNP transistor by E. A. Valsamakis in an article entitled "Lateral PNP with Gain Bandwidth Product", in the IBM Technical Disclosure Bulletin, vol. 13, 1970, pg. 1457. A completely different method has been described for a graded base PNP transistor in U.S. Pat. No. 3,873,989 issued to Schinella et al. However, it is not known how either of these methods can be easily incorporated within an NPN fabrication technology.